The present invention generally relates to the preparation of semiconductor material substrates, especially silicon wafers, which are used in the manufacture of electronic components. More particularly, the present invention relates to a process for thermally treating or annealing one or more silicon wafers to reduce the concentration of metal contaminants such as copper from the wafer interior or bulk. Additionally, the process of the present invention may be performed in a manner that reduces the concentration or size of agglomerated vacancy defects on the surface and in the bulk of one or more silicon wafers.
Silicon device performance is degraded by metallic contaminants. Transition metals, including copper, iron and nickel, may dissolve and diffuse during the normal thermal cycles associated with integrated circuit manufacturing conditions. While cooling from the temperatures associated with integrated circuit manufacturing, copper and other metals may precipitate or concentrate at the surface of the wafer, as well as at interfaces, defect sites, and regions that are doped with, for example, boron (e.g., p-type wafers or regions). These precipitates are generally believed to be the reaction of product the contaminant metals and silicon. In the case of copper, they are believed to be copper silicide precipitates. The precipitates often result in the formation of dislocations and other defects. The precipitates and their associated dislocations and defects, if present in the device fabrication region of the wafer, may render integrated circuits prepared from the wafer useless. Additionally, copper silicide precipitates may form what are referred to as haze defects because, upon being subjected to a common etching treatment and bright light inspection, the precipitates cause defects that appear as a haze on the surface of the wafer. Because of these problems, integrated circuit manufacturers generally require that the concentration of copper on the surface of a silicon wafer be no more than 1×1010 atoms/cm2 to 1×1011 atoms/cm2, as determined by methods standard in the art. Further, it is foreseeable that this requirement will be decreased to a value of 5×109 atoms/cm2, 1×109 atoms/cm2 or less since a large fraction of random device failures can be traced to copper silicide precipitates.
Single crystal silicon wafers are commonly manufactured by a process which starts with the growth of a monocrystalline silicon ingot produced by the Czochralski method or the float-zone method. The crystal ingot is typically sliced into wafers with a wire-saw, the wafers are flattened by lapping and chemically etched to remove mechanical damage and contamination. After being etched, the wafers are polished on one or both sides. Although the wafers may undergo additional processing such as thermal annealing to reduce crystal originated particles, the processing typically ends with state of the art cleaning methods. After such a cleaning, the copper concentration on the surface of polished wafers is typically less than 1×1010 atoms/cm2, as determined by total reflection spectroscopy (TXRF) measurements. See, e.g., C. Neumann et al., Spectrochemica Acta, 10 (1991), pp. 1369–1377; and Ingle & Crouch, Spectrochemical Analysis, Prentice Hall, 1988. The surface copper concentration of these wafers, however, tends to increase with the passage of time even at room temperature until saturation is reached. Thus, wafers which meet a target specification for surface copper concentration immediately after cleaning may fail to meet this specification as soon as five to ten months later.
To date, there have been three main approaches to dealing with the problem of copper contamination of silicon wafers. The first approach includes reducing the amount of copper and other metals that are introduced into the silicon during the polishing operation. Specifically, the industry has primarily focused its attention on identifying and eliminating, to the extent possible, the sources of these contaminants. In addition to reducing the amount of metals in polishing mixtures, other methods such as that disclosed by Prigge et al. (DE 3939661 A1) include limiting the amount copper actually incorporated into the wafer during polishing by admixing with polishing agents certain reagents which form a coordination complex with copper. This coordination complex acts to maintain the copper in a specific conformation which limits the ability of copper to enter the silicon. Although modifying polishing mixtures have tended to reduce the degree of copper contamination in silicon wafers, it typically has not been sufficiently effective to negate the need for other copper reduction methods. Additionally, the ever more stringent limitations being placed upon metallic contaminant levels in silicon wafers by integrated circuit manufactures makes relying on polishing mixture modifications a significantly more costly option for controlling metallic contamination in silicon wafers.
The second approach for dealing with the metal contamination of polished silicon wafers is intrinsic gettering to trap copper and other metals and prevent these metals from reaching the device region of the wafer. Intrinsic gettering techniques involve introducing defect sites into the silicon wafer at locations which do not disturb the functioning of integrated circuits fabricated from the wafer (i.e., a region of the wafer interior below the device region often referred to as the “bulk”, the “wafer bulk”, or the “bulk region”). Gettering techniques, however, have not proven to be an entirely acceptable solution for controlling metallic contaminants. For example, the high diffusivity of metals such as copper and nickel in silicon enables these metals to escape from gettering sites and reach the device region. Additionally, it is possible for the defects introduced into silicon as gettering sinks to reduce the quality of silicon by, for example, reducing minority carrier recombination lifetime.
The third approach for dealing with the problem of metallic contamination of polished silicon wafers is the use of one or more so-called “low temperature anneals” to drive copper from the bulk of a silicon wafer to the surface where it can be removed. For example, Falster et al., U.S. Pat. No. 6,100,167 disclose a process which generally involves subjecting a wafer to a low temperature anneal (e.g., between about 225 and about 300° C.) for a relatively short period of time (e.g., between about 5 minutes and about 1.5 hours) to increase the rate at which copper diffuses to the surface of the wafer. After diffusing to the surface, the copper is removed from the surface by performing a cleaning operation. One or more of these low-temperature anneals, including cleanings to remove the copper, may be performed before a polished silicon wafer is heated to a temperature in excess of 500° C. in order to avoid the formation of copper silicide precipitates. Although these low-temperature anneals may be used to effectively remove copper from a single silicon wafer, they have not been implemented in a typical manufacturing process because they would significantly decrease throughput and would greatly increase the cost of a wafer. For this reason, these low-temperature anneals have been limited to laboratory and testing applications.
In summary, the manufacture of silicon wafers involves a number of steps which are potential sources for the introduction of metallic contaminants, such as wafer polishing. And, in view of the shortcomings of the foregoing methods for preventing or removing the metallic contamination, a need continues to exist for a simple, low-cost, and effective method for removing metallic contaminants from polished silicon wafers that can be incorporated into conventional manufacturing processes without forming harmful precipitates.